RE: [sv-bc] illegal priority if

Thinking from the perspective of the user, what do they want to see?

Again, from the perspective of the user, what is a natural syntax to express their conditions?

From the perspective of the implementer, what is an efficient way to deliver the output desired given the syntax?

One notion that works in my mind is to treat a unique if, coded as for example as:

unique if (a) begin
   a_f();
end 
else if (b) begin
   b_f();
end
else if (c) begin
   c_f();
end
else begin
   d_f();
end


as if it were coded as:

case ({a,b,c}) {
  3'b001: a_f();
  3'b010: b_f();
  3'b100: c_f();
  3'b000: d_f();
  default: begin
	$display($stime,,"Unique If Violation!! More than one term of {a,b,c} is true");
	$stop;
  end
endcase

Another possibility is:

if (!$onehot({a,b,c}) ) begin  // note that is a, b or c is unknown, this will not trigger
	$display($stime,,"Unique If Violation!! More than one term of {a,b,c} is true");
	$stop;
end 
else if (a) begin
   a_f();
end 
else if (b) begin
   b_f();
end
else if (c) begin
   c_f();
end
else begin // this term will be triggered for any unknown in the conditions
   d_f();
end

And, in truth, I have coded designs using the case block myself many times; and furthermore 
(* curmudgeon warning *) I would envision myself continuing to do so, even given this new 
unique if, as:

1) I have much more control over what happens given a violation;

2) I do not believe there is any "raising of level of abstraction" (code size is the same) with the unique if;

3) it is not defined what actually happens to simulation when a unique if is "violated"
	Simulation exists with an error? 
	All lefthand sides of statements in all conditional bodies are driven to "x"?
	A warning message is printed?

4) if one or more conditional terms on the unique if evaluate to "x" or "z", is this a violation? ("x" could be interpreted as an unordered set of 1 and 0, hence one term "x" and another "1" could be two "1"s and hence is a violation.  The effect of x terms in the conditional is not ambiguous in the case block implementation, nor is it ambigous in the $onehot implementation.

Also, I see Francoise's point: there is an implication that the evaluation of the conditions might have some side effects such that order of calculations of the value of the conditions which are supposed to be unique might result in different behaviours, and that the simulator must contemplate this, and preferentially pick an order which results in no contradition.
For example, given:

unique if (f(a)) begin
   a_f();
end 
else if (f(b)) begin
   b_f();
end
else if (f(c)) begin
   c_f();
end
else begin
   d_f();
end

the simulator must pick if possible the order of evaluating f(a), f(b) and f(c) in such a way that only one function evaluation returns true.  Wow! This is hard, and I would argue not really what I would want my simulator to be doing; nor is it something I imagine a synthesis tool could create logic to replicate in hardware; nor would I want to use up area in silicon for such logic!

Michael McNamara
mcnamara@cadence.com
408-914-6808 work
408-348-7025 cell


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of francoise martinolle
Sent: Thursday, January 12, 2006 10:49 AM
To: 'Bresticker, Shalom'; sv-bc@eda.org
Subject: RE: [sv-bc] illegal priority if

 
I do not understand what it means "interleaving evaluation and *use* of the
conditions".
Also what is the meaning of the sentence "unless it can demonstrate a legal
interleaving so that no more than 
one condition is true"?
Does it mean that if I found 1 sequence of evaluation of each condition in
the branches that
does not make more than one condition true, the unique if is correct?

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Thursday, January 12, 2006 8:20 AM
To: sv-bc@eda.org
Subject: [sv-bc] illegal priority if

Question:

1800 10.4 says, 

"A unique if shall be illegal if, for any such interleaving of evaluation
and use of the conditions, more than one condition is true. For an illegal
unique if, an implementation shall be required to issue a warning, unless it
can demonstrate a legal interleaving so that no more than one condition is
true."

What is the meaning of this "illegality"?

Generally, "illegal" means a fatal compile-time error or something similar.
Is that really the meaning here? Or is the meaning simply that a warning (or
error, for strict people) message needs to be issued? 

I hope my question is clear.

Thanks,
Shalom


Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033
I don't represent Intel