RE: [sv-bc] $bits question

Verilog is full of more ways of saying the same thing. I was only
suggesting that to get us to move on. We're not supposed to be
discussing enhancements at this time :).



> -----Original Message-----
> From: Paul Graham [mailto:pgraham@cadence.com]
> Sent: Monday, January 23, 2006 12:01 PM
> To: Rich, Dave
> Cc: mcnamara@cadence.com; Greg.Jaxon@synopsys.com; sharp@cadence.com;
sv-
> bc@eda.org
> Subject: Re: [sv-bc] $bits question
> 
> > I would also support an enhancement at a later date to allow
'parameter
> > typedef'
> 
> Ugh, we surely don't want to allow more ways of saying
> the same thing.  Either change the existing parameter
> type syntax or stick with the old one, but why have both?
> 
> Paul