RE: [sv-bc] FW: [sv-ec] Question on compilation units & compiler directives

 
Hello SV-BC,

As one of the authors of the package and compilation unit areas
of P1800, I believe that the paragraph mentioned below was
overlooked during late edits of compilation unit topics.

Compiler directives have always existed outside the module namespace,
and their behavior in P1364 is well understood.  If we apply the
"one file is one compilation unit" semantics to compiler directives
(described in "b)" early in 19.3), there will be potentially serious
backwards compatability issues with P1364.

I propose that 19.3 should be amended to indicate that compiler
directives always follow the semantics described in "a)" near
the beginning of the section.

I can take the action to create a Mantis item and proposal if
the group is amenable to that.

Regards,
Doug


> 
> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
> LaFlamme, Jamie
> Sent: Monday, January 23, 2006 5:59 PM
> To: sv-ec@eda.org
> Subject: [sv-ec] Question on compilation units & compiler directives
> 
> The following paragraph in section 19.3 pretty much says that compiler
> directives only apply to the end of the compilation unit:
>  
>     "In Verilog, compiler directives once seen by a tool apply to all
>     forthcoming source text. This behavior shall be supported within a
>     separately compiled unit; however, compiler directives from one
>     separately compiled unit shall not affect other compilation
>     units. This may result in a difference of behavior between
>     compiling the units separately or as a single compilation unit
>     containing the entire source."
> 
> Given that the default compilation unit is supposed to be separate
> compilation units for each source file it seems like a painful
> incompatibility with 1364 Verilog.  Given following example files:
> 
> 	file "defines.v":
> 		`define DEBUG
> 
> 	file "top.v"
> 		`ifdef DEBUG
> 		reg enable_debug;
> 		`endif
> 
> If they are compiled together using separate compilation 
> units for each
> file should the DEBUG macro really not be defined in top.v?  What
> happens if a mix of Verilog 2001 and SystemVerilog source files are
> compiled at the same time?
> 
> Thanks for any input,
> -Jamie
> 
> 
>