[sv-bc] FW: [sv-ec] Question on compilation units & compiler directives

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
LaFlamme, Jamie
Sent: Monday, January 23, 2006 5:59 PM
To: sv-ec@eda.org
Subject: [sv-ec] Question on compilation units & compiler directives

The following paragraph in section 19.3 pretty much says that compiler
directives only apply to the end of the compilation unit:
 
    "In Verilog, compiler directives once seen by a tool apply to all
    forthcoming source text. This behavior shall be supported within a
    separately compiled unit; however, compiler directives from one
    separately compiled unit shall not affect other compilation
    units. This may result in a difference of behavior between
    compiling the units separately or as a single compilation unit
    containing the entire source."

Given that the default compilation unit is supposed to be separate
compilation units for each source file it seems like a painful
incompatibility with 1364 Verilog.  Given following example files:

	file "defines.v":
		`define DEBUG

	file "top.v"
		`ifdef DEBUG
		reg enable_debug;
		`endif

If they are compiled together using separate compilation units for each
file should the DEBUG macro really not be defined in top.v?  What
happens if a mix of Verilog 2001 and SystemVerilog source files are
compiled at the same time?

Thanks for any input,
-Jamie