RE: [sv-bc] FW: [sv-ec] Question on compilation units & compiler directives

>- If I specify a file separately, then of course it is treated as a
>separate unit. 
>
>Now, what happens if you run a tool with a "-decompile" switch to get
>the entire design in a single file which you can recompile afterwards?

In Verilog designs, where compiler directives are the only issue,
a combination of `resetall and appropriate directives can be used
between modules as required.  Macros will presumably have been
substituted during compilation, and will not appear in the decompiled
source, so those are not a problem.

In SystemVerilog, a design that is reliant on multiple separate
compilation units is reliant on multiple source files.  There is
no standard way for such a design to be decompiled into a single
source file that can be recompiled to produce an identical design,
with multiple compilation units.  I don't think this was a goal in
the design of compilation units.

The standard does allow tools to use other mappings from source files
to compilation units, but still assumes that the contents of a single
source file are part of only one compilation unit.  Since it doesn't
standardize any such mappings, this statement isn't really meaningful.
Tools don't need permission from the LRM to have a nonstandard mode
where they support nonstandard functionality.

If a tool did want to support the creation of multiple compilation
units from a single source file, it could presumably do so with such
a nonstandard mode.  The mechanism would presumably require something
like a compiler directive that could be embedded in the source to
indicate the end of one compilation unit and the start of the next.

Steven Sharp
sharp@cadence.com