Re: [sv-bc] FW: [sv-ec] Question on compilation units & compiler directives

From: Paul Graham <pgraham_at_.....>
Date: Wed Jan 25 2006 - 03:45:01 PST
> SystemVerilog is *very* different than C++ in terms of what
> constitutes class assignment legality.  C++ ensures that two
> files with the same class hierarchy included via #include represent
> the same types.  Not true in SV.

Just curious why SV is different in this detail from C++.

Paul
Received on Wed Jan 25 03:45:31 2006

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