Re: [sv-bc] FW: [sv-ec] Question on compilation units & compiler directives

Paul, the following is just my opinion on "how we got here".

I'm not sure that anyone set out to be different, but it
does fall out from the way in which SV deals with types,
elaboration, and type equivalence.  In SV, each elaboration of
a type generally gives rise to a new type (parameterized classes
follow slightly different more global rules).  This means that
for a module that declares a type even different instances of the
module end up with different types.  It follows that `include
(which has always been pure textual inclusion) ends up creating
different types for each inclusion of the type.

In C++ (without using rtti) one has to trust that the user
enforces that the inclusion is consistent.  In addition
(in most systems) name mangling and linker requirements
enforce uniqueness of static properties, existence of
vtbls, consistency of method signatures, etc.

It would have been possible to define such a universe for SV,
but the interactions with elaboration are complex and the
type equivalence would have to rely on some global type
visibility which works against the whole point of $unit
scopes, etc.  Parameterized classes do in fact have a
semi-global analysis aspect that interacts with elaboration
in weird and wonderful ways, but even that analysis is
anchored by each elaboration of the parameterized class itself.

Finally, issues related to type parameters, types being
passed around via interfaces, etc. provide other ways of
sharing types (other than in packages).  These features
would also make a C++ like approach significantly more
difficult due to the elaboration time aspects that show up.

Gord.



Paul Graham wrote:

>>SystemVerilog is *very* different than C++ in terms of what
>>constitutes class assignment legality.  C++ ensures that two
>>files with the same class hierarchy included via #include represent
>>the same types.  Not true in SV.
> 
> 
> Just curious why SV is different in this detail from C++.
> 
> Paul

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com