Howard, The structure of generates and the naming rules in 1364-2001 had a number of serious issues involving visibilty, what constituted valid designs, and how to deal with various elaboration issues. There was a very significant effort put into revising that part of the LRM for the 1364-2005 spec. The working groups adopted the revised spec early and have strongly recommended that vendors adopt the 2005 rules rather than the very problematic 2001 rules. Under the 2005 rules, your example design is invalid since the unnamed generate condition does in fact create a new scope. The 2005 rules, while formally standardized with 1364-2005 have been agreed upon rules for quite a while now and at least some vendors have been compliant with the new rules for nearly 2 years. In order to deal with vendors that are not enforcing the 2005 rules, you should ensure that you are using named generate constructs, should ensure that you only use the name once in a scope, and that a generate name cannot possibly conflict with any other identifier. Following those restrictions should result in designs that work for all vendors. As an additional reference point, ModelSim has also followed the committee recommedations in enforcing the 2005 rules and has for quite some time. Thus ModelSim would agree with the Cadence implementation in disallowing this design. Gord. Maidment, Matthew R wrote: > Hi All. > > A question about unnamed generate scopes. > > ------------------------------------------------------------------------ > From: Johny Srouji [mailto:srouji@us.ibm.com] > Sent: Wednesday, February 01, 2006 4:23 PM > To: Howard Long > Cc: Howard Long; Pierre Girouard; Maidment, Matthew R > Subject: Re: Question on IEEE Standard 1364-2001 > > > I am forwarding your note to the proper people who run the technical > committees. > Matt Maidment is the technical chair of the SystemVerilog and > Verilog design modeling and issues/errata committee and I am sure > he'll forward into his group. > > BTW, there is a mailing list: <sv-bc@eda.org> which you can use for > such queries. > > Regards, > > --- Johny. > > > > > "Howard Long" <hcl@logicvision.com> > > 02/01/2006 05:04 PM > > > To > Johny Srouji/Austin/IBM@IBMUS > cc > "Pierre Girouard" <pg@logicvision.com>, "Howard Long" > <hcl@logicvision.com> > Subject > Question on IEEE Standard 1364-2001 > > > > > > > > > Dear Sir: > > I have a question on the IEEE Standard 1364-2001, the Verilog 2001 > standard: > > Should the conditional generate constructs "if-else" and "case" be > treated as anonymous blocks with local scope (two blocks in the if-else > and one for each case item) if the "generate_item" or "genvar_case_item" > enclosed by the construct is not a named "generate_block"? For example, > if a "module_instantiation" is specified as the "generate_item" in an > "if" construct, is that "module_instantiation" invisible to "defparam" > statements? By way of an actual example, if I have the following > Verilog code: > > module top (in1, out1); > input in1; > output out1; > parameter m1 = 1; > defparam i4.p1=2; > generate > if( m1 > 0 ) > joe i4(in1, out1); > endgenerate > endmodule > > module joe(in1, out1); > input in1; > output out1; > parameter p1 = 1; > endmodule > > Should an error message be generated because instance i4 is not visible > at the point of the defparam? I know of at least one vendor which takes > this approach (Cadence Design Systems) and another (Synopsys) which > appears to take the opposite approach (i.e., there is no local scope and > i4 is visible). Has this issue been clarified in any errata or new > revisions of the standard? > > Respectfully, > Howard Long > LogicVision, Inc. > > > -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.comReceived on Thu Feb 2 09:01:55 2006
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