[sv-bc] FW: Question on IEEE Standard 1364-2001

Hi All.
 
A question about unnamed generate scopes.


________________________________

	From: Johny Srouji [mailto:srouji@us.ibm.com] 
	Sent: Wednesday, February 01, 2006 4:23 PM
	To: Howard Long
	Cc: Howard Long; Pierre Girouard; Maidment, Matthew R
	Subject: Re: Question on IEEE Standard 1364-2001
	
	

	I am forwarding your note to the proper people who run the
technical committees. 
	Matt Maidment is the technical chair of the SystemVerilog and
Verilog design modeling and issues/errata committee and I am sure he'll
forward into his group. 
	
	BTW, there is a mailing list: <sv-bc@eda.org> which you can use
for such queries. 
	
	Regards, 
	
	--- Johny. 
	
	
	
	
	
"Howard Long" <hcl@logicvision.com> 

02/01/2006 05:04 PM 

To
Johny Srouji/Austin/IBM@IBMUS 
cc
"Pierre Girouard" <pg@logicvision.com>, "Howard Long"
<hcl@logicvision.com> 
Subject
Question on IEEE Standard 1364-2001

	




	Dear Sir:
	
	I have a question on the IEEE Standard 1364-2001, the Verilog
2001
	standard:
	
	Should the conditional generate constructs "if-else" and "case"
be
	treated as anonymous blocks with local scope (two blocks in the
if-else
	and one for each case item) if the "generate_item" or
"genvar_case_item"
	enclosed by the construct is not a named "generate_block"?  For
example,
	if a "module_instantiation" is specified as the "generate_item"
in an
	"if" construct, is that "module_instantiation" invisible to
"defparam"
	statements?  By way of an actual example, if I have the
following
	Verilog code:
	
	                module top (in1, out1);
	                input in1;
	                output out1;
	                parameter m1 = 1;
	                defparam i4.p1=2;
	                generate
	                if( m1 > 0 ) 
	                                 joe i4(in1, out1);
	                endgenerate
	                endmodule
	
	                module joe(in1, out1);
	                input in1;
	                output out1;
	                parameter p1 = 1;
	                endmodule
	
	Should an error message be generated because instance i4 is not
visible
	at the point of the defparam? I know of at least one vendor
which takes
	this approach (Cadence Design Systems) and another (Synopsys)
which
	appears to take the opposite approach (i.e., there is no local
scope and
	i4 is visible).  Has this issue been clarified in any errata or
new
	revisions of the standard?
	
	Respectfully,
	Howard Long
	LogicVision, Inc.