RE: [sv-bc] FW: Question on IEEE Standard 1364-2001

Hi,

Regarding Synopsys, I believe the Presto Verilog compiler for Design
Compiler has a switch allowing either version to be used. Appendix B of
the Presto manual has a nice description of the differences between the
versions. I don't know about the VCS compiler.

Shalom


> >     Should an error message be generated because instance i4
> is not visible
> >     at the point of the defparam? I know of at least one
> vendor which takes
> >     this approach (Cadence Design Systems) and another
> (Synopsys) which
> >     appears to take the opposite approach (i.e., there is no
> local scope and
> >     i4 is visible).  Has this issue been clarified in any
> errata or new
> >     revisions of the standard?