Date: Wed Feb 22 2006 - 06:52:16 PST
Hi, SV adds to the BNF the ability to follow an endtask, endfunction, endmodule, and endinterface with ": identifier", as described in 10.8 for end at the end of a named block. However, in contrast to 10.8, this ability seems nowhere to be described in the text (except for endinterface), which is significant because it is a change from Verilog. Further, it does not seem to state anywhere that it shall be an error if the identifier following the endxxx does not match the name of the task/function/module/interface. Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
