RE: [sv-bc] endtask/function/module/interface :identifier

Mantis 1354:

SV adds ability to append an identifier name to all sorts of endxxx
statements, in order to note which construct is being ended. 

This appears in BNF, but in most cases, except for 'end' of sequential
named blocks and for 'join' of parallel named blocks, it is not noted in
the text. In some cases, it appears in examples.

Readers should not have to study BNF in order to know that a feature
exists, especially where this is a change from Verilog.

In addition, it is necessary to state in text that it shall be an error
if identifier following 'endxxx' does not match the identifier name at
the beginning of the construct.

The 'endxxx' statements in question are:

endmodule
endinterface
endfunction
endtask
endprogram
endclass
endpackage
endconfig
endproperty
endsequence
endgroup
endprimitive
endclocking

(Of course, need to check the correctness of the list.)

Based on the text of 10.8, similar text could be placed in most places.
A template would be something like,

"SystemVerilog allows a matching block name to be specified after the
endxxx keyword, preceded by a colon. A name at the end of the block is
not required. It shall be an error if the name at the end is different
from the block name at the beginning."

Alternately, this could be described for all of them in one place, maybe
in 10.8.

Also need to cover named generate begin-end blocks.


Shalom