According to 8.4, "In SystemVerilog, operators may be applied to 2-state values or to a mixture of 2-state and 4-state values. The result is the same as if all values were treated as 4-state values and the Verilog operators were applied. In most cases, if all operands are 2-state, the result is in the 2-state value set. The only exceptions involve operators where Verilog produces an X result for operands in the 2-state value set (e.g., division by zero)." I interpret this to mean that if, say, int x, y; then type(x/y) == type(integer) type(x*y) == type(integer) ... Is that interpretation correct? Thanks, -- BradReceived on Mon Mar 13 22:16:26 2006
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