>I interpret this to mean that if, say, > > > int x, y; > > >then > > > type(x/y) == type(integer) > > type(x*y) == type(integer) > > >Is that interpretation correct? Well, the result is a signed 32-bit 4-state vector, but I don't know that it is the same type as "integer". So the answer to the main question is "Yes, it is 4-state." That takes care of the issue that x/y can produce 32'bx if y is 0, and the issue that the Verilog integral operators are only defined for 4-state operands. I'm just not sure that your way of expressing this answer in terms of the type operator and the built-in integer type is valid. Steven Sharp sharp@cadence.comReceived on Tue Mar 14 11:12:35 2006
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