Stu, In the following example does o get i or 3? typedef bit [1:0] T ; module test ( input T i, output T o ) ; always_comb unique case (i) ( o = 0 ) : ; ( o = 1 ) : ; ( o = 2 ) : ; ( o = 3 ) : ; endcase endmodule For a related Verilog example, see http://www.boyd.com/1364_btf/report/full_pr/566.html -- Brad -----Original Message----- From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Stuart Sutherland Sent: Thursday, March 16, 2006 3:37 PM To: sv-bc@eda.org Subject: RE: [sv-bc] Mantis 1345: 10.4: "illegal" unique if/case issues Brad, The behavior I suggested would allow--actually require--every simulator to do the same thing for every "pathological case". a) Look for static overlap of decision select expressions at compile time. b) When entering a decision statement, analyze how many branch select expressions are true at that instant, and warn if multiple or no selections are true. c) Execute the first matching branch (same behavior as today, without a 'unique' modifier. In my mind, the only possible divergence between tools would be due to event ordering for when the decision statement is entered relative to other events in the active event queue at that moment in time. That might lead to a difference in what decision select expressions are true at that moment in time. But, that risk exists today, and always has existed, and affects which branch is the first matching branch. Stu ~~~~~~~~~~~~~~~~~~~~~~~~~ Stuart Sutherland stuart@sutherland-hdl.com +1-503-692-0898 > -----Original Message----- > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On > Behalf Of Brad Pierce > Sent: Thursday, March 16, 2006 2:34 PM > To: sv-bc@eda.org > Subject: Re: [sv-bc] Mantis 1345: 10.4: "illegal" unique > if/case issues > > >Let's not make a mountain out of a molehill! > > Tool implementers don't have the luxury of only handling typical test > cases correctly. We have to handle even the most apparently > pathological test cases correctly. > > -- Brad > > > >Received on Thu Mar 16 16:59:56 2006
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