Re: [sv-bc] Sign-extension of wildcard comparison right operand with wild sign bit

>Is that a correct interpretation of the sentence, and, if so, is that
>the intended behavior?

Yes, and yes.

I wouldn't expect a lot of deliberate wildcard comparisons of values with
mismatched widths, and anyone doing it should know the rules.  The most
likely cases will involve accidental extension.  For example,

  reg signed [2:0] r, mask = 3'sb?10;
  
  r = 3'sb111; 
  if ((r ^ 1) ==? mask)
  
Here you are trying to compare two 3-bit values: (3'sb110 ==? 3'sb?10),
but the use of the 32-bit literal 1 will cause extension to 32 bits first.
If you didn't sign-extend the right operand with wild sign bit, the sign
extension of the left operand would cause the comparison to fail.  With
the sign-extension of the right operand, it succeeds, as it should.  By
sign-extending both operands, if the sign bits matched before extension,
then they will match after extension, regardless of whether the right
operand sign bit was 0, 1 or wild.  This gives the desired effect that
sign-extension does not change the equality relation.  For unsigned
operands, the zero-extension of both also causes them to match if they
matched before.

It would also be messy to specify sign-extension rules that behaved
differently depending on the operator and the value of the sign bit.
For anyone who does want to compare values with mismatched widths, and
needs to know the rules, using the normal rules keeps it easier to
understand and less likely to be surprising.

Steven Sharp
sharp@cadence.com