More comprehensively: 12.2 says, "SystemVerilog allows an array to be specified as a formal argument to a task." 12.3 says, "SystemVerilog allows an array to be specified as a formal argument to a function". 12.3.1 says, "In SystemVerilog, a function return can be a structure or union." There does not seem to be any explicit statement in Section 12 that arguments and function return values can be of any type, so these statements are easily interpreted as excluding other types, otherwise why mention one type and not mention another? In order to avoid such room for misinterpretation, these need to be reworded. Shalom > -----Original Message----- > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of > Bresticker, Shalom > Sent: Thursday, February 16, 2006 3:19 PM > To: Rich, Dave; sv-bc@eda.org > Subject: RE: [sv-bc] tasks and function argument and return types > > What confuses me is that 12.3.1 says, > "In SystemVerilog, a function return can be a structure or union", which > might be interpreted as excluding arrays, for example. > > Shalom > > ________________________________________ > From: Rich, Dave [mailto:Dave_Rich@mentor.com] > Sent: Wednesday, February 15, 2006 12:56 AM > To: Bresticker, Shalom; sv-bc@eda.org > Subject: RE: [sv-bc] tasks and function argument and return types > > There are no restrictions, hence nothing to state. > > ________________________________________ > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of > Bresticker, Shalom > Sent: Tuesday, February 14, 2006 4:44 AM > To: sv-bc@eda.org > Subject: [sv-bc] tasks and function argument and return types > > Hi, > > What data types are legal and illegal as task/function arguments and as > function return types? > > I don't see it clearly stated in the LRM. > > Thanks, > Shalom > > Shalom Bresticker > Intel Jerusalem LAD DA > +972 2 589-6852 > +972 54 721-1033 > I don't represent IntelReceived on Mon Apr 17 07:11:15 2006
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