RE: [sv-bc] 12.4.5 Optional argument list - question

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Mon Apr 17 2006 - 10:39:52 PDT
No, in Verilog the parentheses are required, even if the function has no
arguments.

Shalom

> -----Original Message-----
> From: R.S.Nikhil [mailto:nikhil@bluespec.com]
> Sent: Monday, April 17, 2006 7:46 PM
> To: Michael (Mac) McNamara
> Cc: Bresticker, Shalom; sv-bc@eda.org
> Subject: Re: [sv-bc] 12.4.5 Optional argument list - question
> 
> Mike,
> 
> I agree fully with the sentiment, but I thought
> that this "feature" of optional parentheses was for backward
> compatibility with Verilog.
Received on Mon Apr 17 10:40:49 2006

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