Date: Mon Apr 17 2006 - 22:50:26 PDT
Hi, I saw in the book "SystemVerilog for Design", by Sutherland, Davidmann, and Flake, that "SystemVerilog extends Verilog to allow variables declares within tasks, functions, begin...end blocks, fork...join blocks, or the compilation unit scope to be declared with in-line initial values." E.g., begin int count = 0; ... end Where is this described explicitly in the 1800 LRM text? Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
