Re: [sv-bc] 6.3: Constant variables?

> 6.3 says, “Constants are named data variables that never change. Verilog 
> provides three constructs for defining elaboration-time constants: the 
> *parameter*, *localparam *and *specparam *declarations.”
> 
> This looks a little strange. I understand that in 6.3.5, one might want 
> to think of consts as a special type of variable, but it seems strange 
> to say that a parameter is a variable, even if one that never changes. 
> In what way is it a variable? Even its declaration differs from that of 
> variables.
> 
> Shalom

I agree with Shalom. One might wonder what the difference is between
a parameter and a variable declared with the const modifier.

6.3 should expand on what was said in 6.1:

"Verilog constants are data objects whose value will be invariant
  during simulation or operation of the design.  Constants are:
   - signified by literal values (see clause 3);
   - named by genvars, parameters, localparams, or specparams; or
   - computed at elaboration time by constant expressions or
     generate loop iterators [12.4.1 of IEEE-1364 (2005)]."

"Named constants may take on different values as distinct modules
  or generate schemes elaborate, but they are invariant during the
  lifetime of the scope in which they are declared.
  Parameters in particular, are intended to factor out dimensions or
  properties of a generic design so that they can be systematically varied.
  Localparams and genvars provide additional means to control the
  elaboration of the design network."