Re: [sv-bc] 6.3: Constant variables?

Parameter question for the Verilog old-timers.

I seem to recall that about 10 years ago, Verilog-XL actually allowed 
one to change the value of a parameter on the fly during simulation 
(#10 change a parameter value). It was real odd behavior for 
something that was supposedly a semi-constant.

I just tried it with a couple of other simulators and it is no longer 
permitted. Point is, I thought parameters used to behave like strange 
variables.

Does anyone else remember this behavior or was I eating too many 
"Happy Meals" 10 years ago?  :-)

Regards - Cliff

At 01:42 AM 5/1/2006, you wrote:

>6.3 says, "Constants are named data variables that never change. 
>Verilog provides three constructs for defining elaboration-time 
>constants: the parameter, localparam and specparam declarations."
>
>This looks a little strange. I understand that in 6.3.5, one might 
>want to think of consts as a special type of variable, but it seems 
>strange to say that a parameter is a variable, even if one that 
>never changes. In what way is it a variable? Even its declaration 
>differs from that of variables.
>
>Shalom

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Cliff Cummings - Sunburst Design, Inc.
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