Re: [sv-bc] 6.3: Constant variables?

>I seem to recall that about 10 years ago, Verilog-XL actually allowed 
>one to change the value of a parameter on the fly during simulation 
>(#10 change a parameter value). It was real odd behavior for 
>something that was supposedly a semi-constant.

XL still allows it, though it now produces a nasty warning:

Warning!  Illegal assignment of parameter.  Parameters are                     
          compile time constants and should be treated as                      
          such.  This will be not be allowed in future                         
          releases of Verilog-XL                            [Verilog-PARLHS]
          
Of course, changing the value of a parameter at runtime would not
change any of the structural things dependent on that parameter.

Steven Sharp
sharp@cadence.com