[sv-bc] FW: Can a keyword be used as identifier if context is clear?

I forward this from Ben Cohen.

As I wrote Ben, I know that in 1364-2001, all keywords were illegal in
all contexts. Was this changed in the last-minute change to
configurations in 1364-2005?

Shalom

-----Original Message-----
From: vhdlcohen@aol.com [mailto:vhdlcohen@aol.com] 
Sent: Thu, 11 May 2006 11:02:23 -0400
Subject: [sv-ec]  Can a keyword be used as identifier if context is 
clear?

   I ran into this issue because I used code where the keyword 
"instance" was used as an identifier, and one tool compiled it, while 
another tool rjected it. For example:
 function new(string instance, ..);
  "instance" is a keyword from IEEE 1364 in configurations. From LRM, 
section 13.1:
 config cfg1; // specify rtl adder for top.a1, gate-level for top.a2
 design rtllib.top;
 default liblist rtlLib;
 instance top.a2 liblist gateLib;
 endconfig
  Thus, a compiler can differentiate from the context if "instance" is a

keyword or an identifier.
  The question then becomes: should a tool blindly disallow the use of 
keywords as identifiers, or can a tool use a keyword if the context for 
that keyword is clearly defined?

  
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 Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org
 * Training for VMM, SVA and PSL
  * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 
0-9705394-7-9
  * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd 
Edition, 2004, ISBN 0-9705394-6-0
  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 
0-9705394-2-8
 * Component Design by Example ", 2001 isbn 0-9705394-0-1
  * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 
0-7923-8474-1
  * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 
0-7923-8115
  
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