Hi, All - At 10:07 AM 5/12/2006, Brad Pierce wrote: >Then why not allow only #1step? I have no objection to this de-hancement! Does anybody have a good reason for using #2step or greater? Regards - Cliff > >I already > >tell people that there is no known good reason to use a step value > >other than #1step and that using #2step or greater opens the door to > >potential race conditions. > >-- Brad ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification TrainingReceived on Fri May 12 10:21:37 2006
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