RE: [sv-bc] Is #4.2step legal?

It looks like from the discussion regarding my question, that, at a minimum,
Section 3.5 should be amended to state that either only an integer value can
be used with a time unit of step, or that a fixed point value specified with
a unit of "step" will be rounded off to the time unit that is represented by
step.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
  

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Clifford E. Cummings
> Sent: Friday, May 12, 2006 10:22 AM
> To: sv-bc@server.eda.org
> Subject: Re: [sv-bc] Is #4.2step legal?
> 
> Hi, All -
> 
> At 10:07 AM 5/12/2006, Brad Pierce wrote:
> >Then why not allow only #1step?
> 
> I have no objection to this de-hancement!
> 
> Does anybody have a good reason for using #2step or greater?
> 
> Regards - Cliff
> 
> 
> > >I already
> > >tell people that there is no known good reason to use a step value
> > >other than #1step and that using #2step or greater opens 
> the door to
> > >potential race conditions.
> >
> >-- Brad
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
> 
>