RE: [sv-bc] Is #4.2step legal?

Thanks to Shalom for finding this in the LRM. I believe the LRM is 
fine as is but a forward reference from section 3.5 to section 19.10 
would not be objectionable.

I am not opposed to limiting step to integers and even limiting step 
to #1step. As Jonathan and I have pointed out, neither one of us can 
find a reasonable reason to use anything other than #1step. LRM 
limitations would be acceptable, but in the absence of those codified 
limitations, I think we can all agree that whenever any of us teach 
#1step, we point out that although decimal and non-unit steps are 
permitted, there are no known good reasons to use anything other than 
one step.

Point out that nobody on the SV committees can think of a good reason 
to use any step other than #1step, but that we have not made any 
restrictions (yet!)

Ask users to email us with any methodology that they believe requires 
a non-unit step and allow us the opportunity to suggest an 
alternative coding style.

Whenever I think of any engineer essentially playing with delta 
delays to beat some race condition, I can usually find a flaw in 
their general coding style.

That having been said, having the #1step based on global precision 
(even though there was nothing like it in Verilog) to be 
exceptionally useful in assertions and verification (it really has no 
place, that I can think of, in design).

I still find a number of people writing that #1step is a Preponed 
region sampling, forgetting that typically a clock started the 
timestep. As I recall, there are a couple of places in the LRM that 
accurately describe the #1step as actually sampling in the Postponed 
region of the timestep immediately preceding the #1step-current 
timestep (that could be the smallest global precision or 100's of ns 
earlier). Translation - since nothing happens between the Postponed 
region of the preceding timestep and the Preponed region of the 
current timestep, that is an ideal place to sample everything that 
settled out before the current timestep started.

Regards - Cliff

At 06:17 AM 5/19/2006, you wrote:
>Being as 19.10 explicitly states that step is equal to the global
>precision, I think the intent was obvious. This would be just a minor
>clarification, not fixing a 'huge oversight'.
>
>Shalom
>
> > Steven is right; this is a huge oversight in the LRM. Section 3.5
>needs
> > to define the semantics of the 'step' delay as ignoring all local
> > timescales and precisions and needs to be defined to be the scaled to
> > the smallest global precision.

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