I agree with Shalom on this one. Of course blocking and non-blocking assignments are used to ensure that clocks and data transitions are not coincident. Besides this paradigm there are some rare situations where it is useful to be able to ensure that one signal transitions before another. Using #1step delays all over the place is not something that I would recommend, but just like we see how it is useful to have a #1step delay at the boundary between the testbench and the design, I am sure that there are other places where these types of delays can be useful. Leaving the possibility for values other than 1 is a feature that should be left in the language. I've got to believe that there will be several people that will be able to find useful ways to take advantage of this capability. Using these types of delays at the boundaries of a distributed simulation is one place where they could possibly be useful. Bresticker, Shalom wrote On 05/19/06 06:17,: > I can certainly imagine someone trying to use it to ensure order of > execution, i.e. #1step being executed before #2step. > > Shalom > > >>Can someone *please* explain what on earth they think >>#Nstep is for, given N>1 ? I am completely at a loss >>to imagine any situation in which it is either robust >>or useful. > > -- --------------------------------------------------------------------- Neil Korpusik Tel: 408-720-4852 Senior Staff Engineer Fax: 408-720-4850 Frontend Technologies - ASICs & Processors (FTAP) Sun Microsystems email: neil.korpusik@sun.com ---------------------------------------------------------------------Received on Fri May 19 10:13:47 2006
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