RE: [sv-bc] Is #4.2step legal?

Cliff,

> That having been said, having the #1step based on global precision
> (even though there was nothing like it in Verilog) to be
> exceptionally useful in assertions and verification (it really has no
> place, that I can think of, in design).

[Shalom] So maybe someone would find "2step" to be useful in assertions
or verification as well.


> I still find a number of people writing that #1step is a Preponed
> region sampling, forgetting that typically a clock started the
> timestep. As I recall, there are a couple of places in the LRM that
> accurately describe the #1step as actually sampling in the Postponed
> region of the timestep immediately preceding the #1step-current
> timestep (that could be the smallest global precision or 100's of ns
> earlier). Translation - since nothing happens between the Postponed
> region of the preceding timestep and the Preponed region of the
> current timestep, that is an ideal place to sample everything that
> settled out before the current timestep started.

[Shalom] I find this to be very confusing. See
http://www.eda.org/mantis/bug_view_page.php?bug_id=0001293 .

Quoted there are:

9.3: "Conceptually, this 1step sampling is identical to taking the data
samples in the Preponed region of the *current* time slot." (emphasis
mine)

15.2: "A 1step input skew allows input signals to sample their
steady-state values in the *time step immediately before* the clock
event (i.e., in the *preceding* Postponed region)"

15.12: "If the input skew is not an explicit 0, then the value sampled
corresponds to the signal value at the Postponed region of the time step
skew *time units prior* to the clocking event (see Figure 15-1 in
15.3)." 

To those, I would add:

15.3: "An input skew of 1step indicates that the signal is to be sampled
at the *end* of the previous time step. In other words, the value
sampled is always the signal's last value immediately before the
corresponding clock edge."

Shalom