Re: [sv-bc] Is #4.2step legal?

Doulos and Project VeriPage both have online primers about clocking
blocks

   http://www.doulos.com/knowhow/sysverilog/tutorial/clocking/
   http://www.project-veripage.com/clocking_block_1.php

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Monday, May 22, 2006 8:42 AM
To: sharp@cadence.com; sv-bc@eda.org; shalom.bresticker@intel.com;
Dave_Rich@mentor.com
Subject: RE: [sv-bc] Is #4.2step legal?


>From: "Rich, Dave" <Dave_Rich@mentor.com>

>[DR>] 4. Get rid of it altogether by fixing the construct that required
>it in the first place, clocking blocks.

Stepping back and solving the broader problem sounds good to me.  I just
don't know enough about clocking blocks to propose that.

Steven Sharp
sharp@cadence.com