RE: [sv-bc] Is #4.2step legal?

Regarding anything but #1step ...

At 11:25 PM 5/20/2006, you wrote:
>Cliff,
>
> > That having been said, having the #1step based on global precision
> > (even though there was nothing like it in Verilog) to be
> > exceptionally useful in assertions and verification (it really has no
> > place, that I can think of, in design).
>
>[Shalom] So maybe someone would find "2step" to be useful in assertions
>or verification as well.

Perhaps, but based on exchanges with really smart committee members 
(including yourself), nobody has suggested even a plausible reason 
for using #2step.

I think I mentioned this in an earlier email message, but for all 
practical purposes, we can think of #1step as a delta delay, and the 
only reason to look backward two delta delays is because you expect 
to change something between two delta delays ago and one delta delay 
ago, which seems most odd.

This is why I have suggested that all of us who teach and discuss the 
#1step with anybody should give the strong recommendation to only use 
#1step and never some other #_step, until such time that someone can 
prove that a #2step offers some type of methodology advantage. 
Basically I am challenging the world to come up with a good reason to 
use #2step. If someone finds a good use for it, I will embrace it. 
Until then, I say "don't use it!"

The only time I have ever seen VHDL coders play with delta delays is 
with concurrent signal assignments for clock buffers. There I have 
seen VHDL coders balance the depths of the concurrent signal 
assignment buffers to avoid VHDL-delta-race conditions (we don't have 
this problem with continuous assignments).

>Shalom

Regards - Cliff

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Cliff Cummings - Sunburst Design, Inc.
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