> The only time I have ever seen VHDL coders play with delta delays is > with concurrent signal assignments for clock buffers. There I have > seen VHDL coders balance the depths of the concurrent signal > assignment buffers to avoid VHDL-delta-race conditions (we don't have > this problem with continuous assignments). Agreed, but there is another common use that is also significant for VHDL users: waiting for "0 ns" to allow a signal assignment to take effect, so you can see the settled/resolved value on the signal instead of simply the value you drove. Often useful if you are trying to keep your driving and monitoring code completely separate. I don't think we have that issue in SV, because we have a more complete solution in the clocking construct. Note that #1step is NOT a delta delay. The nearest thing Verilog/SV has to a VHDL delta delay is one trip through the NBA scheduler region, iterating back to the active region. Like VHDL delta, that happens within a single timestep and without moving forward by a "timeprecision" interval. It's easy to pause for one of those delta cycles, without needing to invoke the #1step mechanism: ->>e; @e; // pause for one delta I have a big, big problem with the use of #_step for any purpose other than specifying #1step sampling skew in a clocking. In that context it has a clear and useful meaning that has nothing whatsoever to do with the time resolution. If we use it in procedural code, it introduces a delay **whose value may be affected by code somewhere else in the simulation**. This idea frightens me witless, even when I warp my mind enough to see why I might want to introduce such a time delay. If you wish to share my fear, you may consider the variety of different meanings that the SV LRM ascribes to the word "step". -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Received on Tue May 23 11:06:56 2006
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