RE: [sv-bc] implicit declarations in port expressions

>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>4.5 refers to a "port expression declaration", whereas these are not
>"port expression declarations", but rather "port declarations" or maybe
>"port identifier declarations". No expression is being declared.


The text has to cover cases like

module m(.a({b, c[0], d[3:0]}));
input [3:0] b, c, d;

It needs to specify that it is not talking about a, but is talking
about b, c, and d.  These are the identifiers used in the port
expression {b, c[0], d[3:0]}.  When it talks about the vector width,
it should say that it is the width from the declaration of the
identifier used in the port expression, not the width of the port
expression declaration.

Since it also has to cover cases like

module m(b);
input [3:0] b;

and even

module m(input [3:0] b);

the wording might be easier if it referred to the identifiers that
are being declared in port declarations.  Then there would be no need
to distinguish these different kinds of port lists.  All that matters
is that the identifier was declared as a port in a port_declaration, but
not declared as a net or variable.

But even that has to be stated carefully, since the identifier could
be declared as a net or reg as part of the port declaration, or in a
separate declaration.  So you can't say things like "appearing in a
port declaration but not a net or variable declaration".  It could be
declared as a variable while appearing only in a port declaration,
because of the combined syntax.  You have to say more general things
about not being declared as a net or variable.

Steven Sharp
sharp@cadence.com