RE: [sv-bc] implicit declarations in port expressions

From: Steven Sharp <sharp_at_.....>
Date: Mon Jun 12 2006 - 11:58:08 PDT
>From: "Feldman, Yulik" <yulik.feldman@intel.com>

>So, just to be sure I understand you
>right, my understanding is that the identifier "b" in all 3 following
>examples should be considered an implicit declaration:
>
> 
>
>module m1(b);
>
>input b;
>
>endmodule
>
> 
>
>module m2(.a(b));
>
>input b;
>
>endmodule
>
> 
>
>module m3(input b);
>
>endmodule
>
> 
>
>If this is correct, then there is a need to find a phrasing that will
>unambiguously cover all three.


Yes.  This may not be easy.


Steven Sharp
sharp@cadence.com
Received on Mon Jun 12 11:57:37 2006

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