>From: "Rich, Dave" <Dave_Rich@mentor.com> >Converting an existing Verilog design to 2-state is unlikely to improve >performance by any significant measure. I would have made this same point in my reply, except that he already said that he wasn't expecting much. He may still be expecting more than he will get. Steven Sharp sharp@cadence.comReceived on Mon Jun 12 14:56:20 2006
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