Re: [sv-bc] ordered parameter overrides into named sequential blocks

From: Steven Sharp <sharp_at_.....>
Date: Fri Jun 16 2006 - 12:57:04 PDT
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>From: "Geoffrey.Coram" <Geoffrey.Coram@analog.com>
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>
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>One may declare parameters in a named sequential block in 1364-2005
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>
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>
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>My question is: can one override the parameters declared in the block
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>using an ordered list of overrides, eg,
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>  example #(4, 3.14) inst2();
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No, nor with named overrides.
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>Does this assign the value 3.14 to myscope.p2?
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No.
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>I don't see this specifically addressed by 
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>  12.2.2.1 Parameter value assignment by ordered list
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>but it seems logical to correlate the overrides with the declaration
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>order of parameters, regardless of whether they are declared at 
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>module scope or in a named block.
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Logical or not, that isn't how it works, because that isn't how it
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worked in Verilog-XL.  Overrides at module instantiation can only affect
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parameters declared at the module level.  Parameters inside nested scopes
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can only be overridden using defparams.
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You can complain that this is an ugly nonlocal construct reaching down
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through the hierarchy, but then overriding a parameter declared in a
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nested block is inherently an ugly thing reaching down through the
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hierarchy.  If you want the parameter to be accessible to the module
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instantiation, then it should be declared at the module level.  Declaring
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it in a nested block is effectively a request for it to be hidden.  That
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is what nested scopes do.
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Steven Sharp
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sharp@cadence.com
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Received on Fri Jun 16 12:57:14 2006

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