Re: [sv-bc] parameterized structures

From: Greg Jaxon <Greg.Jaxon_at_.....>
Date: Fri Jun 16 2006 - 12:38:19 PDT
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Gordon Vreugdenhil wrote:
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> There is another important difference -- C++ doesn't have the
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> additional "elaboration" phase that Verilog has and as a result
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> essentially all "template" analysis is a compile time
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> activity. 
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C++'s template instantiation phase is driven by a fixed-point linking
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discipline that is essentially identical to design elaboration.  The
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compiler is not done cranking out template instantiations until no
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new ones are demanded and the last one is specialized.
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> In SV, different elaborations of a parameterized
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> class create different universes for instantiation.
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I don't understand the phrase "different universes for instantiation".
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Of course each parameterization of an SV class, like a C++ template class
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specialization, produces a particular class (a new data type) which then
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governs the behavior of a family of class instances.  That's like a
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universe in which you can construct new instances...
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>  There is no corresponding concept in C++.
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Which could be why I am not recognizing it. Are you sure that brief section
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7.23 is inventing something new under the sun?
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>  One implication of this is
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> that a static pre-elaboration "name mangling" approach as used
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> in C++ can't work in SV.
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Name mangling is nothing more than an encoding of the scope and structural
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info needed to uniquely characterize each type.  The exact rules for type
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identity in SV and in C++ are a bit different, but in both cases there is
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a finite amount of info that must be known before the type comes into existence
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and which can be encoded into a "mangled name".  Mangled names can become
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as interesting as Gödel numbers if you let them.
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If you can prove that no name-mangling approach will ever work for SV,
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then the game is up - the language is simply uncompilable.
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This might be a true statement.  For instance, if the language provides
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a facility for deriving new types on the fly which exploit the differences
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between distinct dynamic objects ( ones created only by the running simulation),
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then those new types could not possibly be compiled during elaboration phase.
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Gödel does have a proof about "incompleteness" of many formal systems.
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But even dynamically invented types can be given unique mangled names - provided
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you found a way to unambiguously encode the identity of the dynamic objects
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that contribute to their definition.
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Classes and structs in SV are *more* different than they are in C++.
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The key element being the automatic dynamic memory management of SV class objects
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which is unlike C++ and is not needed for SV static structs.
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Parameterizing structs does not make them dynamic, however.  So this
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difference is preserved even if struct syntax is extended in this way.
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Greg
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> 
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> Gord.
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> 
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> 
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> Feldman, Yulik wrote:
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> 
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>> What's the difference between this "parameterized" stuff and class 
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>> templates?
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>>
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>> [Yulik] “Parameterized” is a just a Verilog term for the same concept 
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>> which is known as “template” in C++. Even though “class” is a term 
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>> common to both languages, SV uses “parameterized class” terminology, 
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>> instead of C++’s “template class”, probably due to conceptual 
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>> similarity and consistency with the already established Verilog 
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>> terminology based on Verilog 95’s “parameters”.
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>>
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>>
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>> Kev.
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>>
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>>  
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>>
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> 
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Received on Fri Jun 16 12:38:24 2006

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