Re: [sv-bc] parameterized structures

There is another important difference -- C++ doesn't have the
additional "elaboration" phase that Verilog has and as a result
essentially all "template" analysis is a compile time
activity.  In SV, different elaborations of a parameterized
class create different universes for instantiation.  There is
no corresponding concept in C++.  One implication of this is
that a static pre-elaboration "name mangling" approach as used
in C++ can't work in SV.

Gord.


Feldman, Yulik wrote:

> What's the difference between this "parameterized" stuff and class 
> templates?
> 
> [Yulik] “Parameterized” is a just a Verilog term for the same concept 
> which is known as “template” in C++. Even though “class” is a term 
> common to both languages, SV uses “parameterized class” terminology, 
> instead of C++’s “template class”, probably due to conceptual similarity 
> and consistency with the already established Verilog terminology based 
> on Verilog 95’s “parameters”.
> 
> 
> Kev.
> 
>  
> 

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com