RE: [sv-bc] parameterized structures

What's the difference between this "parameterized" stuff and class
templates?

[Yulik] "Parameterized" is a just a Verilog term for the same concept
which is known as "template" in C++. Even though "class" is a term
common to both languages, SV uses "parameterized class" terminology,
instead of C++'s "template class", probably due to conceptual similarity
and consistency with the already established Verilog terminology based
on Verilog 95's "parameters".


Kev.