[sv-bc] parameterized structures

Hi,

 

I would like to get a general opinion of forum's experts on the idea to
introduce parameterized structures to SystemVerilog. Parameterized
structures are similar to regular structures, but allow
parameterization, like modules, classes and interfaces. The syntax
currently doesn't matter, but just to give a visual example:

 

typedef struct #(SIZE = 32, TYPE = integer) {

            bit [SIZE-1:0] m1;

            TYPE m2;

} parameterized_struct;

 

parameterized_struct ps1; // Default parameterization

parameterized_struct #(.SIZE(64), .TYPE(int)) ps2; // Overridden
parameterization

 

The ability to parameterize structures may be quite useful to raise the
abstraction level of the design. It is quite similar to how template
classes/structs in C++ help to raise the abstraction level of C++
programs. Parameterized structures, unlike parameterized modules and
interfaces, will be data types, which will allow their usage in wide
spectrum of coding scenarios (for example as operands of expressions).
Unlike parameterized classes, parameterized structures could be easily
used in design itself (vs. testbench code), without fear to open a can
of worms of object life time and scheduling semantics issues. And, on
top of that, there seems to be no problem to synthesize and/or formally
analyze the parameterized structures. 

 

So, please, let me know what you think about it.

 

Thanks,

            Yulik.