RE: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

SystemVerilog added a new C-like short-circuiting operator '&&&' that's
the topic of

    http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=959

-- Brad

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com] 
Sent: Wednesday, August 02, 2006 5:07 PM
To: sv-bc@eda.org; Brad.Pierce@synopsys.COM
Cc: WADAMS@freescale.com; michael.burns@freescale.com
Subject: Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]


>From: "Brad Pierce" <Brad.Pierce@synopsys.com>
>
>I think Stu is asking for language that's like that used for && and ||.
>They are not required to be short-circuiting.  The short-circuiting is 
>optional only.

Somehow I thought they were required to be short-circuiting.  My
mistake.
Too much C coding.  So there currently aren't any operators that are
required to be short-circuiting.

In Verilog, we can get away with not requiring these things to be
short-circuiting.  Expression evaluation doesn't produce errors in
Verilog, and side-effects are limited to function calls.  It matches the
hardware behavior closely, as Stu suggested.

In SystemVerilog, things like null handle dereferences can produce
run-time errors, and there are assignment operators which have side
effects.  So there may be a stronger desire for short-circuiting, for
use in more software-like code in the testbench.

Steven Sharp
sharp@cadence.com