>From: "Brad Pierce" <Brad.Pierce@synopsys.com> > >I think Stu is asking for language that's like that used for && and ||. >They are not required to be short-circuiting. The short-circuiting is >optional only. Somehow I thought they were required to be short-circuiting. My mistake. Too much C coding. So there currently aren't any operators that are required to be short-circuiting. In Verilog, we can get away with not requiring these things to be short-circuiting. Expression evaluation doesn't produce errors in Verilog, and side-effects are limited to function calls. It matches the hardware behavior closely, as Stu suggested. In SystemVerilog, things like null handle dereferences can produce run-time errors, and there are assignment operators which have side effects. So there may be a stronger desire for short-circuiting, for use in more software-like code in the testbench. Steven Sharp sharp@cadence.comReceived on Wed Aug 2 19:05:07 2006
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