RE: [sv-bc] query about system verilog interfaces

Suman,
 
For why the LRM is silent on such issues, see 
 
      http://www.eda-stds.org/sv-bc/hm/4898.html
<http://www.eda-stds.org/sv-bc/hm/4898.html> 
 
To test your netlist, drive it and the original RTL with the same test
bench.
 
But, yes, your netlist is reasonable except for a missing space in
"\u2.u1.b;"
 
There are syntax errors in your interface instantiations though.  They
should be as follows
 
interface ifc1;
  wire a, b;
endinterface
 
interface ifc2;
  wire x, y;
  ifc1 u1();
endinterface

module top;
  ifc2 u2();
  bot IO (.u(u2));
endmodule

module bot (ifc2 u);
endmodule

-- Brad

________________________________

From: owner-sv-bc@eda-stds.org [mailto:owner-sv-bc@eda-stds.org] On
Behalf Of Suman Nandan
Sent: Tuesday, August 08, 2006 11:11 PM
To: sv-bc@eda-stds.org
Subject: [sv-bc] query about system verilog interfaces


Hello Experts, 
What should be output of the following RTL after systhesis ? 
----------------------------------------------------- 
interface ifc1; 
  wire a, b; 
endenterface 


interface ifc2; 
  wire x, y; 
  ifc1 u1; 
endinterface 


module top; 
  ifc2 u2; 


  bot IO (.u(u2)); 
endmodule 


module bot (ifc2 u); 
endmodule 
------------------------------------------------- 
Should it compile to something like : 
------------------------------------------------ 
module top; 
  wire \u2.x , \u2.y , \u2.u1.a , \u2.u1.b; 


  bot (.\u.x (\u2.x ), .\u.y (\u2.y ), .\u.u1.a (\u2.u1.a ), .\u.u1.b 
(\u2.u1.b )); 
endmodule; 


module bot (inout \u.x , \u.y , \u.u1.a , \u.u1.b ); 
endmodule 
--------------------------------------------------------------------- 
I could not find any lead from the LRM 1800-2005 regarding 
instanciation of interfaces within inerface. 
Can you please help me out ? 


Thanks,
Suman.