[sv-bc] query about system verilog interfaces

Hello Experts,
What should be output of the following RTL after systhesis ?
-----------------------------------------------------
interface ifc1;
  wire a, b;
endenterface

interface ifc2;
  wire x, y;
  ifc1 u1;
endinterface

module top;
  ifc2 u2;

  bot IO (.u(u2));
endmodule

module bot (ifc2 u);
endmodule
-------------------------------------------------
Should it compile to something like :
------------------------------------------------
module top;
  wire \u2.x , \u2.y , \u2.u1.a , \u2.u1.b;

  bot (.\u.x (\u2.x ), .\u.y (\u2.y ), .\u.u1.a (\u2.u1.a ), .\u.u1.b
(\u2.u1.b ));
endmodule;

module bot (inout \u.x , \u.y , \u.u1.a , \u.u1.b );
endmodule
---------------------------------------------------------------------
I could not find any lead from the LRM 1800-2005 regarding
instanciation of interfaces within inerface.
Can you please help me out ?
Thanks,
Suman.