I agree with Will Adams. I would support adding a requirement to the LRM that &&, || and the conditional operator be evaluated with short- circuiting. This didn't really matter much in Verilog, but becomes a serious issue in SystemVerilog with all the side-effects (such as run-time errors) that can occur in expression evaluation. As I wrote earlier, this should not present any problem for synthesis. Any expression where short-circuiting makes a difference will not be synthesizable anyway. Synthesis tools can ignore the requirement, since they will have already disallowed any situation where it matters. Note that if synthesis did have any problem with short-circuiting, it would have the same problem when the user had to rewrite their code with nested if-statements to get the same short-circuiting. The &&& is a kludge that should be eliminated in favor of making && work the way most users would expect. For reference, Verilog-XL appears to short-circuit && and ||, at least in if-statement conditions (and in the situation where it is detectable, i.e. where there is a function call in the right operand). Steven Sharp sharp@cadence.comReceived on Thu Aug 10 12:00:05 2006
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