RE: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

I agree that short-circuit evaluation is highly desirable.
It will provide greater compatability across simulators,
and it will be more consistent with C's precedent.

It sounds like there aren't really any backwards compatability
issues, since previously the precise behavior was undefined.
As someone recently told me, any rule is backwards compatible
with chaos.

Doug 

> -----Original Message-----
> From: owner-sv-bc@server.eda-stds.org 
> [mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Steven Sharp
> Sent: Thursday, August 10, 2006 12:00 PM
> To: sharp@cadence.com; wadams@freescale.com
> Cc: sv-bc@server.eda.org; Brad.Pierce@synopsys.com; 
> michael.burns@freescale.com
> Subject: Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]
> 
> I agree with Will Adams.  I would support adding a requirement to the
> LRM that &&, || and the conditional operator be evaluated with short-
> circuiting.  This didn't really matter much in Verilog, but becomes a
> serious issue in SystemVerilog with all the side-effects (such as
> run-time errors) that can occur in expression evaluation.
> 
> As I wrote earlier, this should not present any problem for synthesis.
> Any expression where short-circuiting makes a difference will not be
> synthesizable anyway.  Synthesis tools can ignore the 
> requirement, since
> they will have already disallowed any situation where it 
> matters.  Note
> that if synthesis did have any problem with short-circuiting, it would
> have the same problem when the user had to rewrite their code 
> with nested
> if-statements to get the same short-circuiting.
> 
> The &&& is a kludge that should be eliminated in favor of 
> making && work
> the way most users would expect.
> 
> For reference, Verilog-XL appears to short-circuit && and ||, 
> at least in
> if-statement conditions (and in the situation where it is 
> detectable, i.e.
> where there is a function call in the right operand).
> 
> Steven Sharp
> sharp@cadence.com
> 
>