RE: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Sun Aug 13 2006 - 05:08:23 PDT
Steven Sharp wrote:

> So which behavior is this small amount of questionable legacy code
> relying on?  Verilog-XL appears to do short-circuit evaluation of
> && and || operators, at least when there are function calls with
> side-effects involved so that it can be tested.  That accounts for
> all the oldest legacy code.  The other Verilog simulator I have
> access to does it also.  There are others that I don't have access
> to, but I would not be surprised if almost all of them do it too.
> Perhaps others can comment on that.

Just one data point: I tried two other simulators, testing &&
and || with both left and right operands being functions with
side-effects that returned a single-bit result, both on the
right-hand side of a procedural assignment and as the test
in an "if" statement.  One consistently applied short-circuit
evaluation, one consistently evaluated both operands every time.

Of course, I cannot promise that this behaviour is reliable 
across every possible combination of compile-time option, 
arrangement of source code, etc.

However, it does emphasise that there are significant
differences in behaviour among mainstream tools, with the
consequence that if short-circuit evaluation were to be 
either outlawed or mandated, at least one simulator would
need to be re-worked (and presumably have a command-line
option added to restore its legacy behaviour).  It also
implies that Brad's distaste for reliance on such behaviour
has strong practical justification.  And it strongly suggests
that there may be some very fragile user code out there, and 
that it might be a very good idea indeed for compilers to 
issue warnings about it.
-- 
Jonathan Bromley, Consultant

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Received on Sun Aug 13 05:08:28 2006

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