Date: Sun Aug 20 2006 - 07:32:23 PDT
I would like to. Shalom ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce Sent: Friday, August 18, 2006 6:56 PM To: sv-bc@server.eda.org Cc: Korchemny, Dmitry Subject: RE: [sv-bc] Mantis 1563: allow to pass macro arguments by name Shalom, Could default macro arguments be specified, similar to 12.4.3? -- Brad ________________________________ From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom Sent: Friday, August 18, 2006 2:54 AM To: sv-bc@eda.org Cc: Korchemny, Dmitry Subject: [sv-bc] Mantis 1563: allow to pass macro arguments by name Fixed an error: I have filed Mantis 1563, an enhancement request to pass macro arguments by name. For consistency, the language is similar to that of 12.4.4 for tasks and functions. In 23.2, INSERT 23.2.1 Argument binding by name SystemVerilog allows arguments to macros to be bound by name as well as by position. This allows specifying the arguments in any order and easily specifying the argument to be passed at the call. For example: `define fun(j, s) $display("%d %s", j, s) The fun macro can be called as follows: `fun( .j(2), .s("yes") ); `fun( .s("yes"), .j(2) ); `fun( 2, "yes" ); If both positional and named arguments are specified in a single macro call, then all the positional arguments must come before the named arguments. Then, using the same example as above: `fun( .s("yes"), 2 ); // illegal `fun( 2, .s("yes") ); // OK Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
