>From: "Rich, Dave" <Dave_Rich@mentor.com> >module test (output A, input B, C); > > reg A; > > wire B, C; >This comes from putting parentheses around the V1995 style input/output >statements . I can understand someone wanting to do this when moving >from V1995 to V2001, but I'm wondering if this would cause a problem in >SystemVerilog. I imagine that it could interfere with those complicated defaulting rules for port lists that were brought up recently. The existing rules may already have some holes with ANSI-C-style port lists. They certainly weren't written to cover all the extra situations that could come up with this mixed syntax. Steven Sharp sharp@cadence.comReceived on Thu Aug 24 17:08:30 2006
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