RE: [sv-bc] assignment to input

 > I personally like the ability to read from outputs, and find other
 > languages that forbid this to be not helpful.  The one clear case where
 > reading from an output is quite useful is in a $display or $monitor of
 > the signals in a module.

Many vhdl designs declare an internal signal to shadow each
output just to get the effect of reading an output.

In principle I think that input and output ports should
correspond to constants and variables.  An input, like a
constant, is read-only, while an output/variable is
read-write.  It may be orthogonal to have a write-only data
object, but I don't think it's useful.

In practice of course verilog allows the writing of input
ports...

Paul