RE: [sv-bc] assignment to input

In SystemVerilog, we tried to overcome this loophole by defining an
input port of a variable as a continuous assignment, and since variables
can only have one CA, an input port could not be coerced to an output or
inout.

However, a change late in the IEEE 1800-2005 LRM made inputs implicitly
default to a wire kind, so that 'input reg a' is now treated as 'input
wire reg a'

I doubt that anyone has implanted this change and would really like to
revert it back to the way it was in 3.1a for this very reason. Wires
should only be used where multiple drivers are required.

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Paul Graham
> Sent: Tuesday, August 29, 2006 11:12 AM
> To: sv-bc@server.eda-stds.org
> Subject: RE: [sv-bc] assignment to input
> 
>  > I personally like the ability to read from outputs, and find other
>  > languages that forbid this to be not helpful.  The one clear case
where
>  > reading from an output is quite useful is in a $display or $monitor
of
>  > the signals in a module.
> 
> Many vhdl designs declare an internal signal to shadow each
> output just to get the effect of reading an output.
> 
> In principle I think that input and output ports should
> correspond to constants and variables.  An input, like a
> constant, is read-only, while an output/variable is
> read-write.  It may be orthogonal to have a write-only data
> object, but I don't think it's useful.
> 
> In practice of course verilog allows the writing of input
> ports...
> 
> Paul